On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit

ABSTRACT

An on-chip system and method for measuring the jitter tolerance of a clock and data recovery loop is disclosed herein. Such clock and data recovery loop determines a clock phase for sampling a data stream on a data line by examining transitions of the data stream.  
     The on-chip system includes a control circuit coupled to the clock and data recovery loop which is adapted to receive an error rate associated with sampling the data stream with the clock phase determined by the clock and data recovery loop. The on-chip system is adapted to delay the clock phase by a predetermined amount one or more times, and to monitor the error rate to determine a maximum delayed clock phase for sampling the data stream, the maximum delayed clock phase representing a right timing signal margin. To determine a left timing signal margin, the disclosed on-chip system is adapted to advance the clock phase by a predetermined amount one or more times, and to monitor the error rate to determine a maximum advanced clock phase for sampling the data stream.

FIELD OF THE INVENTION

[0001] The present invention relates to testing of electronic circuitryand more specifically to an on-chip system and method for measuring thejitter tolerance of a clock and data recovery circuit.

BACKGROUND OF THE INVENTION

[0002] As integrated circuits increase in complexity, systems andmethods must be capable of testing them to their limits, if thefunctionality under expected operating conditions is to be proven. Manyadvanced integrated circuits are operating too fast and are becoming toocomplex to be tested only by external test equipment. In place ofexternal test equipment, more and more testing is being performed bycircuitry implemented on the integrated circuit itself asbuilt-in-self-test (BIST) circuitry. However, as the BIST circuitrybecomes more complex, new systems and methods are needed to assure thatintegrated circuit functions are tested to the full limits they arerequired to operate.

[0003] One type of data receiver used in integrated circuits is capableof receiving data bit signals from an incoming data line withoutrequiring a separate clock signal to be transmitted on a separate linefrom the data line. Such data receiver is known as a clock and datarecovery circuit because the phase and frequency of the clock signal isrecovered from the data line signal(s) along with the transmitted databits.

[0004] A particular requirement of an on-chip data receiver, including aclock and data recovery circuit, is that it be tolerant to signaljitter. FIG. 1 shows bit signals 200 as they appear at the input to areceiver. The bit signals 200 include two complementary signals whichswing at periodic intervals, according to their data content. In suchexample, the bit time, defined as the average time between signaltransitions, is 400 picoseconds (pS). However, due to thecharacteristics of the transmitter and the transmission line, and otherinfluences between the transmitter and the CDR, the signal transitions202 have jitter. The jitter is manifested as a period of time 203 duringwhich the state of the complementary data signals is uncertain becauseof variations in the arrival of the signal transitions. Because of thejitter, the clock signal used to sample the data signal is best adjustedto a phase 204 which lies at the midpoint of the bit time betweentransitions. In operation, this sampling clock signal must becontinually adjusted in phase in order to match the transmitted clocksignal. As the incoming data signal varies, it may often take severalclock cycles to adjust the sampling clock signal to the correct phase atthe midpoint between signal transitions. High frequency signal jitterwhich occurs over fewer clock cycles must be tolerated by assuring thatthere be large enough timing margins between the ideal sampling clockphase 204 at the bit time midpoint, and the jitter in the left and righttransitions of the data signal.

[0005] In order to assure satisfactory operation under expectedconditions, a robust system and method is needed to test the jittertolerance of a clock and data recovery circuit.

SUMMARY OF THE INVENTION

[0006] Accordingly, the present invention provides an integrated circuitincluding an on-chip system and a method for measuring the jittertolerance of a clock and data recovery loop. Such clock and datarecovery loop determines a clock phase for sampling a data stream on adata line by examining transitions of the data stream.

[0007] The on-chip system includes a control circuit coupled to theclock and data recovery loop which is adapted to receive an error rateassociated with sampling the data stream with the clock phase determinedby the clock and data recovery loop. The on-chip system is adapted todelay the clock phase by a predetermined amount one or more times, andto monitor the error rate to determine a maximum delayed clock phase forsampling the data stream, the maximum delayed clock phase representing aright timing signal margin.

[0008] The on-chip system is preferably adapted to determine a lefttiming signal margin, as well, by being adapted to advance the clockphase by a predetermined amount one or more times, and to monitor theerror rate to determine a maximum advanced clock phase for sampling thedata stream.

[0009] An on-chip method of measuring the jitter tolerance of a clockand data recovery loop is provided which includes

[0010] a) determining a clock phase for sampling a data stream on a dataline by examining transitions of the data stream;

[0011] b) delaying the clock phase by a predetermined amount;

[0012] c) sampling the data stream with the delayed clock phase anddetermining an error rate for the sampled data stream;

[0013] d) further delaying the delayed clock phase by the predeterminedamount; and

[0014] e) repeating steps c) and d) zero or more times to determine amaximum delayed clock phase for sampling the data stream, the maximumdelayed clock phase representing a right timing signal margin.

[0015] Preferably, the on-chip method additionally includes advancingthe clock phase by a predetermined amount one or more times, andmonitoring the error rate to determine a maximum advanced clock phasefor sampling the data stream, the maximum advanced clock phaserepresenting a left timing signal margin.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIGS. 1 to 4 illustrate functions, operations, and circuit blocksrepresenting background to the present invention.

[0017]FIGS. 5 and 6 illustrate additional functions, operations andcircuit blocks in accordance with a preferred embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018]FIGS. 2 through 4 illustrate features of an on-chip system whichis described as background to the present invention, but is not admittedto be prior art. FIG. 2 is a block diagram illustrating a clock recoveryloop portion 10 of a clock and data recovery circuit (CDR), for use inrecovering the clock phase of a data signal from a transmission linewithin an integrated circuit. The clock recovery loop is a phase lockloop (PLL) which includes a voltage controlled oscillator 20 whichgenerates a clock signal 22 which is phase adjusted to sample the datasignal 24 from the transmission line. To acquire and maintain phaselock, the generated clock signal 22 is provided as a feedback input,together with the data signal 24, to the bang-bang phase detector 26,which provides up and down phase control inputs to a charge pump 28. Thecharge pump 28, in turn, is coupled to a loop filter 30 which provides acontrol input to the VCO 20 to complete the clock recovery loop.

[0019]FIG. 3 is a schematic diagram illustrating the detailed structureof an exemplary bang-bang phase detector 126, such as can be used as thebang-bang phase detector 26 in the clock recovery loop 10 shown inFIG. 1. The bang-bang phase detector 126 examines the transitions of adata signal 124 from a transmission line together with the clock signal122 generated by a VCO 20 in the loop to produce digital outputs foradjusting the clock phase. The bang-bang phase detector 126 gets itsname from the fact that it provides up/down outputs for adjusting theclock phase, up or down, by a discrete amount, rather than as acontinuously variable phase function. The output PDUP adjusts the clockphase by a discrete, predetermined amount upward, and the output PDDNadjusts the clock phase by a discrete, predetermined amount downward.

[0020]FIG. 4 is a block diagram which illustrates elements of an on-chipserial data transceiver, together with additional elements fordetermining a bit error rate of transceiver elements. As shown in FIG.4, a transmitter portion 320 of the transceiver includes a serializer304, which serializes parallel data from either a parallel data inputstream 322 or a repeating pseudo-random bit sequence from a bit errorrate transmit macro (BERTTX) 300, as selected by BERT multiplexer 302.Serialized data is passed to a transmitter phase lock loop (TXPLL) macro306, which in turn passes the data serially to serial driver 308. TheTXPLL macro 306 also establishes a clock signal 307 used to clock dataout from serializer 304. Serial driver 308 then drives serial data oncomplementary serial data output lines (SDO).

[0021] As also shown in FIG. 4, a receiver portion 330 of thetransceiver includes a receiver 310 coupled to receive signals oncomplementary serial data input lines (SDI). Receiver 310 can beimplemented, for example, by a liner amplifier which may have fixedgain. In normal operation, the output of receiver 310 is provided to areceiver clock and data recovery (RXCDR) macro 314 through WRAPmultiplexer 312. The RXCDR macro 314 samples the output signal fromreceiver 310 to recover a serial data bit signal 317 from serial datainput lines SDI and the clock phase, as represented by clock signal 315.The recovered data bit signal 317 and clock phase 315 are passed todeserializer 316 which then provides output as a parallel data stream324.

[0022] The data transceiver shown in FIG. 4 also provides for abuilt-in-self-test (BIST) mode, which tests the bit error rate betweentransmitter portion 320 and receiver portion 330. In such mode, known,as a “serial wrap” test, the BERT multiplexer 302 selects and passes apseudo-random bit sequence output of the BERTTX macro 300 through thetransmitter 320, and the WRAP multiplexer 312 selects and passes thetransmitter output, from the TXPLL macro 306, to the receiver 330. Thetransmitted pseudo-random bit sequence is recovered and deserialized bythe RXCDR macro 317 and deserializer 316, respectively, and thenprovided as a parallel data output stream 324 to a bit error ratereceiver macro (BERTRX) 318. The BERTRX macro 318, having circuitry forlocally generating a replica of the pseudo-random bit sequencetransmitted from the BERTTX macro 300, checks the received data streamfor errors and reports an error rate to a BIST controller (not shown).

[0023] Unfortunately, for several reasons, the jitter tolerance of thereceiver portion 330 cannot be effectively tested during a serial wraptest. First, the transmitted signal has little jitter because it islocally wrapped directly from the transmitter portion 320 to thereceiver portion 330, without being transmitted across serial data linesSDO and SDI, and therefore, has not been subjected to the distortions ofthe transmission channel. Second, the sample clock 122 of the clock anddata recovery circuit 126 is phase locked to the data signal 124, and isalso phase-adjusted to the midpoint 204 of the bit time (FIG. 1). Thus,the system illustrated in FIG. 4 does not test, and has no provision fordetermining the actual left and right timing signal margins 210, 212between the midpoint 204 and the left and right signal jitter,respectively.

[0024] Accordingly, the present invention proposes to modify thebang-bang phase detector 126 described above relative to FIG. 3, suchthat the phase of the sample clock 122 is adjusted incrementally, bydiscrete predetermined amounts, to test the jitter tolerance of thereceiver 330. In so doing, the left and right timing signal margins 210,212 (FIG. 1) are determined. As illustrated by FIG. 5, in the methodprovided by the invention, the sample clock phase is delayed from themidpoint 204, by a predetermined discrete amount (205). A pseudo-randombit sequence is then transmitted from BERT generator 300 to BERTreceiver 318, and the bit error rate of the system is then checked. Ifthe bit error rate is zero, or is within an acceptable limit, then theright timing signal margin 212 has not yet been reached. In such case,the sample clock phase is then delayed by twice the predetermineddiscrete amount 205 as measured from the midpoint 204, and the bit errorrate is then checked again. If the bit error rate is still zero orwithin an acceptable limit, the right timing signal margin 212 has stillnot been reached. The sample clock phase is then delayed again, thistime by three times the predetermined discrete amount 205, as measuredfrom the midpoint 204. The bit error rate is then checked again. Thisprocess continues until reaching a phase 206 which corresponds to aright timing signal margin 212. Beyond the right timing signal margin,the jitter becomes apparent by an unacceptable increase in the bit errorrate. In such manner a maximum delayed clock phase is determined, thatphase corresponding to a right timing signal margin 212.

[0025] A similar process is performed to determine a left timing signalmargin 210. In this case, the sample clock phase is advanced from themidpoint 204, by a predetermined discrete amount (209). A pseudo-randombit sequence is then transmitted from BERT generator 300 to BERTreceiver 318, and the bit error rate of the system is then checked. Ifthe bit error rate is zero, or is within an acceptable limit, then theleft timing signal margin 210 has not yet been reached. In such case,the sample clock phase is then advanced by twice the predetermineddiscrete amount 209 as measured from the midpoint 204, and the bit errorrate is then checked again. If the bit error rate is still zero orwithin an acceptable limit, the left timing signal margin 210 has stillnot been reached. The sample clock phase is then advanced again, thistime measured by three times the predetermined discrete amount 209 fromthe midpoint 204. The bit error rate is then checked again. This processcontinues until reaching a phase 208 which corresponds to a left timingsignal margin 210. Beyond the left timing signal margin, the jitterbecomes apparent by an unacceptable increase in the bit error rate.

[0026] The addition of the right timing signal margin 212 to the lefttiming signal margin 210 together makes up the jitter tolerance of thedata transceiver (FIG. 4). It will be understood that the right timingsignal margin 212 determined under test may not be the same as the lefttiming signal margin 210. This could be the case, for example, if thenominal phase of the sample clock 122 were not centered at the midpoint204. From such determination, one might infer that a static phase erroris present in the transceiver. A static phase error might be caused, forexample, by a current imbalance in the charge pump 28 or by leakage inthe loop filter 30 (FIG. 2).

[0027]FIG. 6 illustrates a modified bang-bang phase detector 626 whichis adapted to advance or delay the phase of a sample clock 122 by apredetermined discrete amount each time, in order to facilitate themethod described above with reference to FIG. 5. Bang-bang phasedetector 626 includes the following additional functions, in addition tothe functions and circuit blocks of bang-bang phase detector 126described above with reference to FIG. 3: a bang-bang control macro 628,and multiplexers 612 and 614. The bang-bang control macro 628 providescontrol outputs BBUP and BBDN, for adjusting the phase of the sampleclock 122 up or down, respectively, by a predetermined discrete amount.The BBSEL output of bang-bang control macro 628 causes multiplexers 612and 614 to select the BBUP and BBDN outputs, at appropriate times, asthe UP and DN outputs of the bang-bang phase detector 626. In addition,the bang-bang control macro 628, receives a signal BERTERR, representingthe bit error rate detected by the BERTRX macro 318 during a serial wraptest.

[0028] In operation, the bang-bang control macro 628 is activated duringa serial wrap test to force shifts in the phase of the sample clock 122which is used to sample serial data as received by the RXCDR macro 314of receiver 330 (FIG. 4). Thus, in an exemplary embodiment, testingbegins with the BERTTX macro 300 generating a pseudo-random bitsequence, which is passed by BERT MUX 302 to serializer 304, and thentransmitted serially on through TXPLL macro 306, through WRAP MUX 312and then to RXCDR macro 314, of which bang-bang phase detector 626 formsa part. The BBSEL output of bang-bang control macro 628 is initiallydisabled for a sufficient time to allow sample clock 122 to become phaselocked to the incoming serial data signal from WRAP MUX 312. After suchtime, the sample clock 122 will have a phase set to the midpoint 204 ofthe bit time, as described above with reference to FIG. 5.

[0029] The bang-bang control macro 628 then activates the BBSEL and BBDNoutputs to begin testing the jitter tolerance of the transceiver (FIG.4), beginning with testing a right timing signal margin 212. The BBSELoutput is activated while the BBDN output is activated, in order toforce a delay in the sample clock phase from the midpoint 204 by apredetermined discrete amount (205). The BBSEL output is thendeactivated, and the bang-bang phase detector 626 is permitted tooperate normally again, such that it begins to acquire, or acquiresphase lock again with the data signal 124, which is provided from theBERTTX macro 300. The bit error rate of the system is then checked byBERTRX macro 318 and the results signaled back to the bang-bang controlmacro 628. If the bit error rate is zero, or is within an acceptablelimit, then the right timing signal margin 212 has not yet been reached.

[0030] In such case, the bang-bang control macro 628 forces a delay inthe phase of the sample clock 122 again, this time by activating BBSELand BBDN for sufficient time to delay the sample clock phase by twicethe predetermined discrete amount 205, as measured from the midpoint204. Thereafter, the BBSEL and BBDN signals are deactivated, and normaloperation of bang-bang phase detector 626 resumes again, at which timethe bit error rate is checked again by the BERTRX macro 318, and resultssignaled back to the bang-bang control macro 628.

[0031] If the bit error rate is still zero or within an acceptablelimit, the right timing signal margin 212 has still not been reached.The sample clock phase is then delayed again by activating the BBSEL andBBDN signals, this time by three times the predetermined discrete amount205, as measured from the midpoint 204, and then deactivated again, suchthat normal operation of bang-bang phase detector resumes 626. The biterror rate is checked again. This process continues until reaching aphase 206 which corresponds to a right timing signal margin 212. Beyondthe right timing signal margin, the jitter becomes apparent by anunacceptable increase in the bit error rate. In such manner a maximumdelayed clock phase is determined, that phase corresponding to a righttiming signal margin 212.

[0032] A left timing signal margin 210 is determined by operationanalogous to that described immediately above, except that the BBSELoutput is activated together with the BBUP output, instead of the BBDNoutput, such that the sample clock phase is advanced by predetermineddiscrete amounts from the midpoint 204 on each pass, until a maximumadvanced clock phase is determined, that phase corresponding to a lefttiming signal margin 210.

[0033] While the invention has been described herein in accordance withcertain preferred embodiments thereof, those skilled in the art willrecognize the many modifications and enhancements which can be madewithout departing from the true scope and spirit of the presentinvention, limited only by the claims appended below.

What is claimed is:
 1. An integrated circuit including an on-chip systemfor measuring the jitter tolerance of a clock and data recovery loopwhich determines a clock phase for sampling a data stream on a data lineby examining transitions of said data stream, said on-chip systemcomprising: a control circuit coupled to said clock and data recoveryloop, adapted to receive an error rate associated with sampling saiddata stream with said clock phase, and adapted to delay said clock phaseby a predetermined amount, whereby said control circuit is adapted todelay said clock phase by said predetermined amount one or more times,and to monitor said error rate, to determine a maximum delayed clockphase for sampling said data stream, said maximum delayed clock phaserepresenting a right timing signal margin.
 2. The integrated circuit ofclaim 1 wherein said control circuit is further adapted to advance saidclock phase by said predetermined amount one or more times, and tomonitor said error rate, to determine a maximum advanced clock phase forsampling said data stream, said maximum advanced clock phaserepresenting a left timing signal margin.
 3. The method of claim 1wherein said control circuit is further adapted to repetitively delaysaid clock phase by said predetermined amount until said received errorrate becomes non-zero, said maximum delayed clock phase being determinedfrom the last delayed clock phase at which said received error rate iszero.
 4. The method of claim 1 wherein said control circuit is furtheradapted to repetitively advance said clock phase by said predeterminedamount until said received error rate becomes non-zero, said maximumadvanced clock phase being determined from the last advanced clock phaseat which said received error rate is zero.
 5. An on-chip method ofmeasuring the jitter tolerance of a clock and data recovery loop,comprising: a) determining a clock phase for sampling a data stream on adata line by examining transitions of said data stream; b) delaying saidclock phase by a predetermined amount; c) sampling said data stream withsaid delayed clock phase and determining an error rate for saidsampling; d) further delaying said delayed clock phase by saidpredetermined amount; and e) repeating said steps c) and d) zero or moretimes to determine a maximum delayed clock phase for sampling said datastream, said maximum delayed clock phase representing a right timingsignal margin.
 6. The method of claim 5 further comprising: f) advancingsaid clock phase by a predetermined amount; g) sampling said data streamwith said advanced clock phase and determining an error rate for saidsampling; h) further advancing said advanced clock phase by saidpredetermined amount; and i) repeating said steps g) and h) zero or moretimes to determine a maximum advanced clock phase for sampling said datastream, said maximum advanced clock phase representing a left timingsignal margin.
 7. The method of claim 6 further comprising determiningan eye width from said maximum delayed clock phase and said maximumadvanced clock phase.
 8. The method of claim 7 wherein said step c) isrepeated until said received error rate becomes non-zero, said maximumdelayed clock phase being determined from the last delayed clock phaseat which said received error rate is zero.
 9. The method of claim 6wherein said steps c) and d) are repeated until said received error ratebecomes non-zero, said maximum delayed clock phase being determined fromthe last delayed clock phase at which said received error rate is zero,and said steps g) and h) are repeated until said received error ratebecomes non-zero, said maximum advanced clock phase being determinedfrom the last advanced clock phase at which said received error rate iszero.